ADN Semiconductors Ltd.

• Bachelor of Science (BSc) in EEE/ECE, EEE, ECE, Electrical Engineering, Electronics Engineering or a related engineering discipline.

• 3 to 5 years

• High-speed ADC design, including SAR and time-interleaved SAR ADC architectures
• Analog front-end design for ADC-based SerDes receivers
• Transistor-level circuit design and simulation
• Comparator, sampling front-end, track-and-hold circuit design
• Reference and bias circuit design
• Clock distribution and timing-skew calibration
• CTLE, AFE and receiver termination design
• Hands-on experience with advanced FinFET process technologies
• Full design flow experience from transistor-level design and simulation through signoff
• Post-layout simulation, verification and performance analysis
• Industry tape-out experience with high-speed ADCs or SerDes receivers
• Experience with Cadence or Synopsys analog/mixed-signal design flows

• Mobile bill,Weekly 2 holidays,Insurance
• Lunch Facilities: Partially Subsidize
• Festival Bonus: 2